• Products
• Investors
• News
• Company Info
• Contact Sales

My Zarlink: Sign In

Pb-free / ROHs info

Zarlink's Pb-Free/RoHS Strategy

 

Zarlink Semiconductor maintains a policy of environmental awareness and responsibility and in so doing we continue to lead with manufacturing strategies consistent with the best practices in the industry. Improvements in our production processes include the elimination of certain chemicals from our products and partnership with contractors who demonstrate compliance with the appropriate environmental standards. Zarlink Semiconductor has made available 'Pb-Free' products to support customers who require them to comply with the EU RoHS directive.

 

Other Zarlink customers have utilized an exception to the above directive which permits them to continue to use Pb in their products for a limited time, until 2010. In consideration of this exemption expiration date, Zarlink Semiconductor is now completing the migration of all leadframe based products to a fully compatible material set with lead plating changed to matte tin. All of the Zarlink leadframe based products with a matte tin finish are backwards compatible with the traditional SnPb solder processes. 

 

Zarlink is also currently developing a roadmap for the conversion of the BGA based packages to an environmentally friendly material set with a solder ball composition of tin/silver/copper (SAC).

 

All new Zarlink products are designed in accordance with environmentally friendly practices and in future, designs utilizing Pb will no longer be available.

 

RoHS Implications

 

The European Union directive Restriction of Hazardous Substances (RoHS) defines specific hazardous materials that must be eliminated by July 2006.

 

Of the six listed "hazardous" materials Hg, Cr6+, Cd, PBB, PBDE are either absent from or only present as trace impurities in the integrated circuits supplied by Zarlink Semiconductor.

 

The sixth material, Pb has been used in the devices terminals of the majority of plastic assembled integrated circuits that have been manufactured over the last 50 years.

 

In support of the environmental requirements Zarlink is producing Pb-free IC devices and all of these are compliant with the Restriction of Hazardous Substances directive. Zarlink certifies the material content of its IC devices with an "Environmental Declaration".

Device Terminals

 

Zarlink Semiconductor has chosen Matte (Pure) Tin as its replacement for SnPb the plating of leaded devices**. Matte (Pure) Tin plating is favoured by the majority of IC manufacturers, assembly subcontractors and customers for many of the leaded package families. Matte Tin is supported by well proven manufacturing processes with one subcontractor being in full production for over 5 years.

** MT90810AK alone uses SnBi plating, the Pb-free reflow conditions defined below are equally applicable.

 

Matte Tin plating has been qualified by our Assembly Subcontractors as being compatible with both high temperature (245-260°C) Pb-free solder reflow and conventional low temperature (220-240°C) SnPb solder reflow profiles. These assembly subcontractors all utilise a post plating bake as a whisker mitigation process.

 

Zarlink Semiconductor has chosen Sn /Ag/Cu as its replacement for SnPb as used for the ball grid packages**. Sn /Ag/Cu is being adopted as the industry "standard" for the balls of these package types. Sn /Ag/Cu is not compatible with the low temperature (205-220°C) SnPb solder reflow profiles which are typically used with PBGA's.

** SnAg ball composition is used for Zarlink bumped die, the Pb-free reflow conditions defined below are equally applicable. 

Reflow Temperature

 

To be compatible with Pb-free IC packages need to withstand a higher reflow temperature, i.e. up to 260°C for the smaller package types. To achieve this, the Assembly Subcontractors are introducing alternative packaging materials, i.e. mould compounds and die attach adhesives that have properties appropriate for higher temperature soldering temperatures.

 

Therefore all RoHS compliant products supplied by Zarlink Semiconductor will be qualified to withstand these higher reflow temperatures as warranted by our subcontractors. In general, Zarlink Semiconductor is using the Classification Reflow profile as defined in table 5.2 of JEDEC J-STD -020 for both lead-frame and ball grid packages.

Zarlink Qualification Programs

 

For all new product introductions the Zarlink policy is to utilise a package material set that is appropriate for Pb-free use and to apply qualification testing accordingly.

 

Zarlink has a progressive program to re-qualify package families and assembly subcontractors with a package material set that is appropriate for Pb-free use and complies with the EU directives on Restrictions of Hazardous Substances (RoHS). The status of these programs is as follows:

 

* SOIC, SSOP and QSOP completed
* QFN completed
* PLCC completed
* QFP completed
* PBGA and HSBGA completed

 

Availability of Pb-free Products

 

Zarlink has now launched Pb-free versions for many of its products and they can be identified in the "Lead-free Selector Guide" on zarlink.com.

 

If your specific product need is not shown on zarlink.com with a Pb-free version as available please contact your local Sales Office who will then establish Zarlink's plan for launching this.

Pb-free Product Identification

 

To ease the transition to using Pb-free versions, the part numbers have been kept very similar to those of the standard versions. For the Pb-free version just one character is modified or added e.g. 

 

Standard	Pb-free
ZL10312QCG >>>	ZL10312QCG1
ZL50409GDC >>>	ZL50409GDC2

 

The one character that has been modified is a package assembly option and product name as shown on the part marking will remain unchanged. However to facilitate identification of Pb-free version these have part marking modified with the inclusion the JEDEC recommended "Pb-free category symbol"

Symbol denotes Matte (Pure) Tin Plate.
Symbol denotes Tin/Silver /Copper.

 

Zarlink is adopting the key requirements of the JEDEC standard JSD97 "Marking, Symbols and Labels for identification of Lead (Pb) Free Assemblies, Components and Devices". Accordingly Zarlink will be applying the JEDEC recommended "2nd Level interconnect label" as an additional packing label. The format of this label is shown below:

 

 

-	The categories are e3 for Sn - Matte (Pure) Sn, e6 for SnBi, e1 for SnAgCu or e2 for SnAg. These are the 4 Pb-free finishes that Zarlink is currently implementing
-	The maximum safe temperature is 260°C. This is the peak temperature which Zarlink is using to qualify its products as per JEDEC J-STD-020B